The goal of this project was to design a 32-bit adder to use a minimal amount of energy per operation with, a maximum delay of 3ns. We used a square-root carry select topology. Our design was notable for its small area, 264um by 83um (including 43um for buffers) with a .25um feature size, the smallest layout in the class.
Report for part 1 available in ps or doc. Also, circuit diagrams for the cells and the whole adder. Finally, images of layouts for the cells and the whole adder are available in doc
Also available are the circuits (for SUE), and the layouts (for MAX). The zip files include SPICE decks used to simulate the adder for timing and power consumption.