Lecture Summary from Spring 2004 -- Provided for reference purposes only. The lectures in Spring 2005 will not necessarily follow the same order/content as that below.
(Readings listed below in the entry for a lecture may actually correspond to multiple lectures in the vicinity of that lecture.)

  1. 1/21/04: Handout distributed. Introduction to the course. Switching algebra. Perfect induction.
    Reading: Sections 2.1 through 2.8 (much of this will be covered in the next lecture)
  2. 1/23/04: Perfect induction. Theorems. De Morgan's law. Duality. Decimal specification. Designation number. Fundamental sum and products (max terms and min terms). Canonical sum and product. Complete sets.
  3. 1/26/04: Reed-Muller canonical form. Set algebra. K maps. Inequalities (meaning of "function f implies function g", implicants of a function). Analyzing NAND and NOR networks ("moving bubbles" to simplify the circuit analysis). Homework 1 assigned (see web page for the class).
    Reading: Sections 3.1 through 3.5, and 6.1 through 6.4
  4. 1/28/04: NAND/NOR networks with fan-outs (section 3.4). Switch networks (section 3.5). K-maps, prime implicants, distinguished 1-cells, prime implicants, complete sum, minimal sum (section 6.3)
    Reading: Sections 6.4, 6.5, 6.6.
  5. 1/30/04: K-maps of 5 and 6 variables. Prime implicant (P.I.) and essential prime implicants. Prime implicants and essential P.I.s for functions with don't cares. Quine-McCluskey tabular procedure for determining P.I.s (to be continued in next lecture)
  6. 2/2/04: Quine-McCluskey tabular procedure for determining P.I.s, finding minimal sum using prime implicant table. Homework 2 assigned today.
    Reading: Section 6.7
  7. 2/4/04: Distinguished column. Essential row. Prime implicant table. Dominating rows. Dominating columns. Secondary essential rows. Petrick's method.
    Reading: Section 6.8
  8. 2/6/04: Functions with don't cares -- determining prime implicants, and minimal sum. First Tison method for determining prime implicants (handout to be distributed in next class).
  9. 2/9/04: Multiple output prime implicants (MOPI). Using K-maps or tabular method to obtain MOPIs. Multiple output minimal cost implementation. Homework 3 posted today.
    Reading: First Tison method (handout distributed in class today -- "alternate" form discussed on page 3 of  the handout not required for the tests), Material on multiple output circuitts from Sections 6.5, 6.6, 6.8
  10. 2/11/04: Minimal multiple-output two-level (AND-OR) circuits using prime implicant table. Graded homework 1 returned today.
    Reading: Chapter 5 (discussion to be started next lecture)
  11. 2/13/04: Multiple output circuit minimization concluded. Symmetic functions. Functions positive and negative in their variables. Residues.
    Reading: Chapter 5
  12. 2/16/04: Unate functions. Threshold functions. Homework 4 assigned today.
    13. Reading: Section 3.6 (to be started next lecture)
  13. 2/18/04: Simple disjoint decomopsition. Boolean difference. Transient analysis of combinational circuits - hazards. Graded homework 2 returned today.
  14. 2/20/04: Static hazard. Dynamic hazards. 0-sets, 1-sets, stable sets, unstable sets. Identification of static hazards.
    Reading: Section 6.10
  15. 2/23/04: Labeling. Marked logic diagram. S-sets and P-sets. Identification of dynamic hazards.
  16. 2/25/05: Marked logic diagram. Identification of dynamic hazards using P-sets and S-sets. Function hazards.
    Material covered in class or assigned for reading through 2/26/04 will be included for test 1. You may bring 1 two-sided sheet  (standard 8.5  inch x 11 inch size) of handwritten notes to the test.
  17. 2/27/04: Hazard-free two-level circuits. Testing of combinational circuits. Stuck-at faults. Bridging faults. Exhaustive testing. Equivalence classes of faults. Minimal test sets.
    Reading: Sections 6.10, 6.11, 6.12
  18. 3/1/04: Tests for stuck at faults in combinational circuits: Boolean difference method, and path sensitization.
    Reading: Sections 7.1 through 7.5.
  19. 3/3/04: Path sensitization. Chapter 7 begins: fundamental mode circuits. SR and D latch. Set-dominant latch. Reset-dominant latch. Gated latch.
  20. 3/5/04: Binary decision diagrams: Lecture by Prof. Janak Patel. 
    Reading:     Graph-Based Algorithms for Boolean Function Manipulation, Randal Bryant, IEEE Transactions on Computers, August 1986.
  21. 3/8/04: No lecture.
  22. 3/10/04: Lecture by Prof. Michael Loui: Moore and Mealy machines. Converting between Moore and Mealy machines. Minimizing number of states.
    Reading: Notes based on Prof. Loui's lecture.
    Additional notes from a previous offering of the course (page 1, page 2, page 3).
  23. 3/12/04: No lecture today on account of Engineering Open House.
  24. 3/15/04: Determining whether machine M1 is contained in M2. Equivalent machines. Experiments. Preset and adaptive experiments. Identification. Synchronizing sequence. Distinguishing sequence.
    Reading: Handwritten notes
  25. 3/17/04: Test 1 in class.
  26. 3/19/04: Preset distinguishing sequence. Adaptive distinguishing sequence.   (Next week is Spring Break)
  27. 3/29/04: S-R latch. D-latch. Gated latch. Symbols for set/reset dependence. Symbol for gated latch. Static hazards in D-latch. Analysis of sequential circuits using latches: input state, latch variables, input variables, total state, excitation functions, excitation table.
    Reading: Sections 7.1 through 7.5. Click here for handwritten slides used in class.
  28. 3/31/04: Anlaysis of sequential circuits using latches. Stable states. Races and critical races. Transition table. Output table. State table. Flow table. Analysis of sequential circuits with feedback loops. (This material is primarily in sections 7.4, 7.5-2, 7.5-3, 7.6)
    Click here for handwritten slides used in class.
  29. 4/2/04:
  30. 4/5/04: Graded test 1 returned in class today. D-flip flop, JK flip-flop, T flip-flop. Essential hazards.
    Reading: Sections 7.6, 7.7. 7.8
    Click here for handwritten slides used in class.
  31. 4/7/04: Essential hazards. Synchronous sequential circuits.
    Click here for handwritten slides used in class.
    32. Reading: Sections 8.1, 8.2-1, 8.2-2
  32. 4/9/04: Synchronous sequential circuits.
  33. 4/12/04: Impossible specifications. Array method for determining indistinguishable states, and equivalence classes for completely specified machines. Incompletely specified machines.
    Reading: Sections 9.1-1, 9.1-2, 9.1-5, 9.1-6, 9.2
  34. 4/14/04: Incompletely specified machines. Pair table. Compatible states. Maximal compatibility classes. Mininal state reduced machine.
    Reading: Section 9.4
  35. 4/16/04: Test 2 (in class).
  36. 4/19/04: Pair table, maximal compatibility classes, reduced machines: more examples of incompletely specified machines
    Reading: Sections 9.1-1, 9.1-2, 9.3
  37. 4/21/04: Incompletely specified machines: example to show that minimal reduced machine may have to be formed using compatibility classes that are not maximal. Sequential circuit synthesis (state or internal variable assignment, flip-flop application table, excitation tables)
  38. 4/23/04: Testing of compbinational circuits with multiple outputs. Additional outputs to increase circuit testability. Built-in self-test, testing using random test vectors.
    Reading: Sections 10.6-1, 10.6-2.
  39. 4/26/04: Built-in self-test (LFSR), Teaching evaluations
    40. Reading: Sections 10.4-1, 10.3 (pages 427-428)
  40. 4/28/04: Graded test 2 returned. Regular expressions.
  41. 4/30/04: Preset and adaptive homing experiment. Checking experiment.
    42. Reading: Handwritten notes
  42. 5/3/04: Distinguishing experiments. State assignment in asynchronous circuits. Don't cares in flow/transition tables in asynchronous circuits.
    43. Reading: Section 9.5
  43. 5/4/04: A review session held on May 4 (Tuesday) from 5:00 to 6:30 p.m. in room 151 Everitt Lab. The review session makes up for time lost due to the lecture assigned for originally scheduled test 1.
  44. 5/5/04: (Last day of classes)